Physical Design and Evaluation of Low Power CMOS Full Adders

摘要

This paper evaluates some low power adder circuits, SERF (9), 10T-I, 10T-III (14) and a complementary adder (28T) at physical layout level. Simulations based on the extracted adder circuit layouts are runt o assess how variou scircuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem, which is not addressed in (9)(14) are also examined. Differences among these adders are addressed and applications of these adders are suggested.