Two-Dimensional MOSFET Dopant Profile by Inverse Modeling via Source/Drain-to-Substrate Capacitance Measurement

摘要

This paper proposes and demonstrates a new approach to 2-dimensional dopant profile extraction for MOSFET's by treating the source/drain-to-substrate junction as a gated diode. The small-signal capacitance of the diode measured as a function of gate and source/drain bias is used as the target to be matched in an inverse modeling process. It is shown that this capacitance allows both the substrate dopant profile in the channel region and the source/drain-to-substrate profile parallel to the surface to be evaluated with a single set of measurement data. Experimental results for n-MOSFETs with drawn channel length = 1 μm is presented. Comparison of other electrical measurement with simulation data based on the extracted profile is also given.