A 940MHz data-rate 8Mb CMOS SRAM

摘要

An 8Mb CMOS SRAM cycles at 470MHz and provides a data rate of 940MHz when run in the double-data rate (DDR) mode. Improved redundancy minimizes SRAM latency, enabling 3.4ns access time. The HSTL I/O performance is enhanced by using flip-chip C4packaging and by decoupling the I/O supply on-chip. The 8Mb SRAM is architected to allow both X18 and X36 organizations, as well as a 4Mb cut-down.