From I_(DDQ) Fault Detection to Defect Localization in Logic CMOS Integrated Circuits: Key Issues

摘要

I_(DDQ) testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, I_(DDQ) testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with I_(DDQ) testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal I_(DDQ) current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of I_(DDQ) testing for fault detection and some key issues regarding localization of the corresponding defect: 1. Appropriate techniques, 2. Switching from electrical testing to fault localization, 3. Modifying the test pattern to shorten the localization process, 4. Constructing a localization method based on an I_(DDQ) diagnostic.