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CMOS Integrated Circuit Fault Detection System

机译:CMOS集成电路故障检测系统

摘要

The tester 1 repeatedly applies the tester pattern to the CMOS integrated circuit 4 in the tester and the power source unit 5 applies the tester pattern to the CMOS integrated circuit 4 through the current detector 6, And supplies current to the circuit (4). The current detector 6 outputs a detection signal connected to the power spectrum analyzer 8 via the amplifier 7 to drain the power spectrum. When the CMOS integrated circuit 4 fails, a static supply current separated from the transistor switching current is generated every predetermined (NT + T) seconds in a certain subpattern in the test pattern. The determining section 9 detects the power of the detection signal out of 1 / (NT + T) and thus determines the static current. That is, the CMOS integrated circuit 4 under test determines a failure.
机译:测试仪1将测试仪图案反复施加到测试仪中的CMOS集成电路4上,电源单元5通过电流检测器6将测试仪图案施加到CMOS集成电路4上,并将电流提供给电路(4)。电流检测器6输出经由放大器7连接到功率谱分析器8的检测信号以消耗功率谱。当CMOS集成电路4发生故障时,在测试图案的某个子图案中每预定(NT + T)秒产生与晶体管开关电流分离的静态电源电流。确定部分9从1 /(NT + T)中检测出检测信号的功率,从而确定静态电流。即,被测CMOS集成电路4确定故障。

著录项

  • 公开/公告号KR970062716A

    专利类型

  • 公开/公告日1997-09-12

    原文格式PDF

  • 申请/专利权人 가네꼬 히사시;

    申请/专利号KR19970003788

  • 发明设计人 사까구찌 가즈히로;

    申请日1997-02-06

  • 分类号G01R31/28;

  • 国家 KR

  • 入库时间 2022-08-22 03:16:20

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