I/sub ddq/ secondary components in CMOS logic circuits preceded by defective stages affected by analogue type faults

摘要

Certain physical failures produce abnormal voltages at the output of the defective stages. I/sub ddq/ testing techniques are shown to be efficient in testing for these failures. Because of the intermediate analogue output of the faulty stage, posterior fault-free stages exhibit abnormal values of I/sub ddq/, increasing the effect of the fault. The set of stages influenced by the fault is modelled and analysed presenting characteristics of the propagation of the influence.