III-V compound semiconductor MOSFETs using Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as gate dielectric

机译：III-V复合半导体MOSFET使用GA / SUS 2 / O / SUB 3 /（GD / SUB 2 / SU / SUB 3 /）作为栅极电介质

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

We report a III-V based metal oxide semiconductor field effect transistor (MOSFET) technology using Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as the gate insulator. Enhancement-mode p- and n-channel, depletion-mode n-channel GaAs MOSFETs, and enhancement-mode n-channel In/sub 0.53/Ga/sub 0.47/As MOSFETs were demonstrated.

机译：我们通过作为栅极绝缘体的GA / SUB 2 / O / SUB 3 /（GD / SUB 2 / O / SUB 3 /）报告基于III-V基于VIS的金属氧化物半导体场效应晶体管（MOSFET）技术。增强模式P-and N沟道，耗尽模式N沟道GaAs MOSFET和增强模式N沟道/亚/亚0.53 / GA / SUB 0.47 /作为MOSFET。

著录项

来源
《Annual Gallium Arsenide Integrated Circuit Symposium》|1997年||共4页
会议地点
作者
Ren F.; Hong M.; Institute of Electric and Electronic Engineer;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类自动化技术、计算机技术;
关键词

相似文献

外文文献
中文文献
专利

1. Negative growth of garment export in guangdong suspended [J] . 无中国对外贸易：英文版 . 2009,第012期
2. Dry etching device quality high-K Ga_xGd_yO_z gate oxide in SiCl_4 chemistry for low resistance ohmic contact realisation in fabricating III-V MOSFETs [J] . X. Li, H. Zhou, R.J.W. Hill, Microelectronic Engineering . 2010,第5a8期

机译：采用SiCl_4化学工艺的干法刻蚀质量高的Ga_xGd_yO_z栅极氧化物，可在制造III-V MOSFET时实现低电阻欧姆接触
3. A novel technique exploiting C-V, G-V and I-V simulations to investigate defect distribution and native oxide in high-kappa dielectrics for III-V MOSFETs [J] . Sereni G., Larcher L., Vandelli L., Microelectronic Engineering . 2015,第NOVa1期

机译：一种利用C-V，G-V和I-V模拟来研究III-V MOSFET高kappa电介质中的缺陷分布和原生氧化物的新技术
4. Analysis of gate tunnelling currents in nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) with SiO_2 and high-K gate dielectrics [J] . G Joshi, M Singh, M Chauhan Proceedings of the institution of mechanical engineers . 2010,第n1期

机译：具有SiO_2和高K栅极电介质的纳米级金属氧化物半导体场效应晶体管（MOSFET）中的栅极隧穿电流分析
5. III-V compound semiconductor MOSFETs using Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as gate dielectric [C] . Ren, F., Hong, Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1997. Technical Digest 1997., 19th Annual . 1997

机译：使用Ga / sub 2 / O / sub 3 /（Gd / sub 2 / O / sub 3 /）作为栅极电介质的III-V型化合物半导体MOSFET
6. Investigation of MOS Interfaces with Atomic-Layer-Deposited High-k Gate Dielectrics on III-V Semiconductors. [D] . Suri, Rahul. 2010

机译：使用III-V半导体在原子层上沉积高k栅极电介质的MOS接口的研究。
7. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure [O] . Szu-Hung Chen, Wen-Shiang Liao, Hsin-Chia Yang, 2012

机译：具有纳米堆叠的高k栅极电介质和3D鳍形结构的高性能III-V MOSFET
8. Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs [O] . Moran, D.A.J., Hill, R.J.W., Li, X., 2007

机译：亚微米，金属栅极，高ε电介质，无植入，增强型III-V mOsFET
9. III-V Compound Semiconductor Native Oxide Mosfets With Focus on Interface Studies. [R] . Hall, D. C., Snider, G. L., Bunker, B. A. 2001

机译：III-V化合物半导体天然氧化物mosfets专注于界面研究。

III-V compound semiconductor MOSFETs using Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) as gate dielectric

摘要

著录项

相似文献

相关主题

期刊订阅