Experimental and analytical studies on CMOS scaling in deep submicron regime including quantum and polysilicon gate depletion effects

摘要

To study CMOS scaling and develop analytical equations to predict future CMOS performance with device and voltage scaling in deep submicron regime, MOSFETs and CMOS ring oscillators fabricated with 2.5 to 6nm T/sub ox/, and channel length down to 0.2/spl mu/m were characterized at 1.5 to 3.3V to confirm the analytical expressions for I/sub dsat/ and gate delay. Based on the experimental and analytical investigation on the fabricated MOSFETs and ring oscillators with wide ranges of T/sub ox/ and L/sub eff/ at various V/sub dd/, I/sub dsat/ and t/sub pd/ can be accurately modeled and predicted from the electrical oxide thickness and universal mobility model.