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A low-power enable/disable GaAs MESFET differential logic

机译:低功耗启用/禁用GaAs MESFET差分逻辑

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In this work, a novel and straightforward enable/disable GaAs MESFET Differential Logic (EMDL) structure is presented. EMDL is compatible with DCFL and some reported MESFET differential logic families, like DPTL, DCVS and DC/sup 2/FL. No power dissipation during the standby state, fewer transistors per logic function and noise immunity are its more interesting features. The EMDL can be efficiently applied in both synchronous and asynchronous designs. EMDL iterative network micropipeline applications are detailed. An 8-bit ripple carry adder was successfully fabricated and tested verifying the EMDL functionality and performance characteristics.
机译:在这项工作中,提出了一种新颖和简单的启用/禁用GaAS MESFET差分逻辑(EMDL)结构。 EMDL与DCFL和一些报告的MESFET差分逻辑系列兼容,如DPTL,DCV和DC / SUP 2 / FL。在待机状态下没有功耗,每个逻辑功能的晶体管较少,噪音抗扰度是其更有趣的功能。可以在同步和异步设计中有效地应用EMDL。 EMDL迭代网络微普通应用是详细的。成功制作了8位纹波携带加法器并测试验证EMDL功能和性能特征。

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