Complementary heterostructure FET (CHFET) standard cells were developed in order to have a low-risk design approach to digital integrated circuits requiring low power and high clock speed (300 MHz to 1 GHz). The circuits take advantage of the very high n-channel transistor gain by using n-channel-rich circuit structures. The complementary cells are simultaneously faster and six times lower in AC power than Si CMOS with the same gate length. Additional CHFET cells with a DC power of 0.6 mW provide even faster speed for circuit critical paths.
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