A new analytical delay model for the BiCMOS inverter is presented. The model is valid in both the low-level and high-level injection regimes, and includes capacitances neglected by other models. The model describes accurately the bipolar transistor in all regions of operation, as well as properly accounts for the nonlinear characteristics of the pMOS in the linear region of operation. The model can be used to estimate both the pull-up and pull-down times and is therefore valid to estimate the 50% rise time as well as the 90% rise and/or the 10% fall time.
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