Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling

摘要

The degradation of delay time of totem-pole BiCMOS, CBiCMOS, and BiNMOS circuits by supply voltage reduction is evaluated by a novel delay-time model. It has been found that base-collector capacitance plays a greater role in determining the delay time than other parasitic capacitances in BiCMOS circuits. It is concluded that when the input signal swings fully from zero to the supply voltage, the minimum supply voltage to guarantee high-speed operation over CMOS circuits is almost the same for the three kinds of BiCMOS circuits. When the input swing is reduced by the base-emitter voltage, however, BiNMOS and CBiCMOS circuits can operate on a lower supply voltage than totem-pole BiCMOS circuits.