VLSI design rules require existing LSI design rules to extend to sub-micron and half-micron geometries. Using high resolution resist and 5$MUL stepper (G- line) technology along with a Post-Exposure Bake (PEB) is a common method to improve the resolution. The PEB drives out residual photoresist solvents which can interfere with the develop process, resulting in CD variations. PEB strongly influences CD variations. The authors consider the following PEB parameters in this CD improvement study: (1) altering the PEB temperature, (2) altering the PEB time, and (3) altering the queuing time between PEB and cool prior to develop. The process characterization data includes critical dimension data for 0.8 $mu@m lines, including proximity effects data on four high-resolution photoresists.
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机译：VLSI设计规则需要现有的LSI设计规则来扩展到子微米和半微米几何形状。使用高分辨率抗蚀剂和5 $ MUL步进（G-LINE）技术以及暴露后烘焙（PEB）是提高分辨率的常用方法。 PEB驱出可以干扰发育过程的残留光致抗蚀剂溶剂，导致CD变化。 PEB强烈影响CD变化。作者在该CD改进研究中考虑以下PEB参数：（1）改变PEB温度，（2）改变PEB时间，（3）在开发之前改变PEB和凉爽之间的排队时间。过程表征数据包括用于0.8 $ MU @ M线的关键尺寸数据，包括关于四个高分辨率的光致抗蚀剂的邻近效应数据。
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