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Multi-flip chip on lead frame overmolded IC package: a novel packaging design to achieve high performance and cost effective module package

机译:铅框架上的多倒装芯片超模封装:一种新型包装设计,实现高性能和经济高效的模块包

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摘要

Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of different levels of voltage and current on a common silicon substrate with controller IC operating in the range of several volts and milliamps, while power MosFETs at over hundreds of volts and more dozens of amps can also pose as an issue. Nevertheless, module packages having controller IC and power MosFET co-packaged are new. Fairchild semiconductor's advancement in packaging has eliminated these drawbacks with the introduction of multi-flip chip on lead frame over-molded IC package. This new package has a novel packaging concept that uses multi-flip chip technology on the power devices combined with controller IC employing wire bonding technique on one copper lead frame based substrate. The gate and source in power MosFETs are bumped and attached to the copper lead frame by flip chip bonding technology and are routed out of package by solder balls while the drain exposed at the bottom of the package is soldered directly to the board. This is a BGA package with exposed die back for drain. The paper describes the construction of multi-flip chip on lead frame over molded package in Fairchild Semiconductor, its cost effective package designs and manufacturing challenges.
机译:小型化可降低封装尺寸,成本和载板空间。芯片上的系统(SOC)将系统集成在公共硅衬底上,但是具有这种方法存在一些缺点,例如高制造成本。使用控制器IC在几伏和毫安的范围内操作不同级别的电压和电流电压和电流,而超过数百伏的功率MOSFET和更多数十个放大器也可以作为一个问题。然而,具有控制器IC和功率MOSFET共同打包的模块包是新的。 Fairchild Semiconductor在包装的推进中消除了这些缺点随着在引线框架上采用过模制的IC包装上的多倒装芯片而消除了这些缺点。该新包具有新颖的包装概念,该概念在一个基于铜引线框架的基板上使用电力器件上的多倒装芯片技术与电源装置相结合。功率MOSFET中的栅极和源极通过倒装芯片键合技术撞击并附接到铜引线框架,并且通过焊球排出包装,而在封装底部暴露的漏极直接焊接到板上。这是一个带有暴露的模具的BGA封装,用于排出。本文介绍了在飞孔半导体中的引线框架上的多倒装芯片的构建,其具有成本效益的包装设计和制造挑战。

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