Co-Design of a High Performance 12-Bit 8GHz DDR4 Switch on a Laminate-Based CSP (Chip Scale Packaging) Technology

摘要

Multiplexer/switch ICs are key components of NVDIMM architecture that serve to isolate the host controller from the DRAM memory system. Signal integrity performance of the IC can drastically be impacted by package parasitics. In this paper we detailed a system co-design methodology that was employed to design a cost-effective DDR4 switch packaged in a laminate-based chip-scale packaging (CSP), without compromising electrical performance. The co-design simulation methodology is validated through correlation to laboratory measurements on TI's TS3DDR4000TM -- a high performance 12-bit 8GHz DDR4 switch.