29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

摘要

Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage $left(V_{mathrm{dd}}ight)$ domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1–5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive $V_{{{mathrm {dd}}}}$ margining. Operation at an elevated $V_{{mathrm {dd}}}$ -and, therefore, the load-current $left(I_{ {{mathrm {load}} }}ight)$ - inflates power draw and further reduces system efficiency $left(eta_{{{mathrm{system}}}}ight)$, i.e. the ratio of the useful (margin-free) output power to input power draw.