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Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement
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机译:混合晶体取向CMOS结构,用于自适应阱偏置以及功率和性能增强
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摘要
The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.
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