Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation

著录项

• 来源
  《电子学报（英文版）》 |2017年第1期|128-131|共4页
• 作者

  LI Jie; WAN Xing; WU Jianbing; SHAN Weiwei;

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• 作者单位

  National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China;

  National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China;

  National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China;

  National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China;

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• 原文格式 PDF
• 正文语种 eng
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