Our goal is to transform a low-level circuit design into a more abstract representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equivalent gatelevel representation. This work focuses on taking that gate-level sequential circuit and performing a temporal analysis which abstracts the clocks from the circuit. The analysis generates a cycle-level gate model with the detailed timing abstracted from the original circuit. Unlike other possible approaches, our analysis does not require the user to identify state elements or give the timings of internal state signals. The temporal analysis process has applications in simulation, formal verification, and reverse engineering of existing circuits. Experimental results show a 40%-70% reduction in the size of the circuit and a 3X-150X speedup in simulation time.
展开▼
