Automatically determining test patterns for a netlist having multiple clocks and sequential circuits

摘要

A method and computer system for automatically determining test patterns for a netlist having multiple clocks and sequential circuits. The invention utilizes a static model of a sequential circuit and models the sequential circuit having multiple clock signals (e.g., one model is used for all multiple clock signals). The multiple clock signals include primary clock input signals and internal clock signals. The clock signals can be gated or dual edge. The invention makes use of the "iterative array representation of sequential circuits" (IAR) model for automatic test pattern generation (ATPG) but utilizes a static sequential circuit model. The invention receives user defined input clock signal waveforms and determines a cycle of clocks based thereon that statically represents all waveforms over time. The cycle of clocks is divided into frames where each frame contains stable clock values. The stable clock values are used to determine the values of each signal that clocks a sequential circuit of the netlist for each frame. This information is then used to determine which sequential circuits are active and which are not active for any given frame. The IAR model is then given the active/inactive information and the ATPG process uses this information to prune efficiency in the search space and search time for finding test patterns that can distinguish a particular fault. Unlike conventional ATPG processes, test pattern determination efficiency is gained in the present invention by having, in advance, the input clock signals given by the user.