In order to increase performance, circuit designers are beginning to use more aggressive timed circuit designs instead of traditional synchronous static logic designs. Recent design examples have shown that significant performance gains are achieved when these aggressive circuit styles are used. Correct operation of these aggressive circuit styles is critically dependent on timing, and in industry they are typically designed by hand. To synthesize and verify timed circuits, the reachable state space of the circuit under the timing constraints needs to be explored. However, complete state space exploration is an exponential problem. State space explosion limits timed circuit designs to small sizes.; enables modular design of large scale timed circuits. It attacks the state space explosion problem by avoiding the generation of a flat state space for the design. Instead, it partitions a design into blocks with manageable sizes, and performs synthesis and verification process on each of them. The results for the blocks are integrated as the solution to the whole design. This dissertation presents a series of theorems that supports modular synthesis and verification. dissertation presents techniques to partition a design and safe net reductions to simplify the complexity when designing each block. Results show that design processes using this method are orders of magnitude more efficient in design time and memory usage.
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