首页>
外国专利>
Circuit synthesis and - verification, taking into account of the relative time response
Circuit synthesis and - verification, taking into account of the relative time response
展开▼
机译:考虑到相对时间响应,电路综合和验证
展开▼
页面导航
摘要
著录项
相似文献
摘要
A system and method of synthesizing and/or verifying a circuit from a behavioral description of that circuit. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then synthesized and/or verified as a function of the modified behavioral description.
展开▼