A manufacturable 0.4 μm process for high-performance LSIcircuits

摘要

To increase the performance of GaAs LSI digital circuits, a new0.4 μm fabrication process is developed which demonstrates excellentyields for E/D logic circuits of up to 5000 gates. The refractoryself-aligned gate process uses stepper-compatible 1 μm lithography.An n+'/buried-p structure results in excellent thresholdvoltage uniformity for a 0.4 μm gate length, with σV_T as low as 8 mV over 3" wafers. Die-sort yields for a16×16-bit multiplier chip are typically better than 55%, and ashigh as 88%. For a 20×20-bit multiplier chip, yields have been ashigh as 61%. Multiplication times of 3.6 ns for the 16×16-bit and4.5 ns (46 ps/gate) for the 20×20-bit multiplier have beenmeasured, representing the fastest room-temperature operation yetreported for such multipliers. LSI fabrication process, yieldevaluation, and circuit performance are described