In accordance with continuing push for smaller and faster electronics, there is strong demand for further miniaturization and higher performance of mobile and other digital devices. Three-dimensional interconnect with through silicon via is the most potential solution to extend Moore's Law. In recent years, 3D interconnect(3DIC) technology is attracting the interest of university, research institutes, Fab engineers, package engineers, chip designers and equipment manufacturers turn to 3D research and development efforts. It has the potential to be the mainstream for chip manufacturing of in the near future. This technology had the benefits of cost, performance, form factor and heterogeneous integration for chips manufacturing. But thermal dissipation, process technology and infrastructure readiness still are the top three issues for success of 3DIC. Cost and manufacturability will be the key knob to enable this technology. In this paper, we demonstrated a production worthy 3DIC technology with IC Fab infrastructure. Key modules' process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity. For the first time, a cost effective wafer thinning without decreasing effective area by a proprietary process is described. Chains were formed between two wafers through bonded copper structures and electrically probed on the top wafer which had been thinned. Yielding 20K through silicon vias with aspect ratio of 15:1 and resistance of through silicon via chain are demonstrated.
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