Efficient utilization of hierarchical iJTAG networks for interrupts management

摘要

Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for different reasons. For example, fault/event occurrences or measurement read-out requests; however iJTAG networks are inherently master/slave networks, where the instruments are the network slaves. In this work, a scalable interrupts-management methodology is presented for allowing instruments-initiated communication using hierarchical iJTAG networks. The presented method allows for an efficient access of the network according to the required use-case by allowing the network to be configured into a corresponding optimized mode. In addition, a novel on-chip localization methodology is presented, which significantly reduces the localization time of interrupting instruments as compared to previous works.