A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain

摘要

A novel CMOS process architecture comprising of 1.5 nm equivalent oxide thickness (EOT) oxideitride (O/N) gate dielectric, self aligned shallow trench isolation (SASTI), dual poly/W gate and W cladded source/drain is shown to have low gate dielectric leakage with excellent boron blocking, no dopant cross-diffusion and lower gate and source/drain parasitic resistance.