首页> 外文会议>European Design and Test Conference, 1996. EDTC 96. Proceedings >Analysis of ISSQ/IDDQ testing implementation and circuitpartitioning in CMOS cell-based design
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Analysis of ISSQ/IDDQ testing implementation and circuitpartitioning in CMOS cell-based design

机译:ISSQ / IDDQ测试实现及电路分析基于CMOS单元的设计中的分区

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Difference between ISSQ and IDDQ testing strategies is presented,discussing the dependency of area overhead and sensing speed on thetechnology. The current sensor implementation style suitable forcell-based design methodology or semi-custom design style is proposedExperimental results for each strategy are discussed. Finally, differenttypes of partitioning strategies are showed, taken into account theparallelism of the gates
机译:介绍了ISSQ和IDDQ测试策略之间的区别, 讨论区域开销和感测速度对 技术。当前的传感器实现样式适合 提出了基于单元的设计方法或半定制设计风格 讨论了每种策略的实验结果。最后,不同 显示了分区策略的类型,并考虑了 门的并行性

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