CMOS cell and circuit design for improved IDDQ testing

摘要

A CMOS cell and circuit design methodology for improved IDDQ testing for logic and memory circuits. The CMOS cell library includes one or more CMOS cells, each including one or more PMOS and NMOS transistors. Each CMOS cell is configured to assert its outputs high during a high test portion of a test mode in which each input is asserted high. Each CMOS cell is configured to assert its outputs low during a low test portion of the test mode in which each input is asserted low. At least one CMOS cell of the library includes one or more test transistors, each test transistor receiving one of first and second test inputs. The test inputs indicate a normal mode, a high test mode and a low test mode. In this manner, each CMOS cell is configured so that each gate oxide interface of each transistor of the CMOS cell receives a test voltage during the test mode. A CMOS circuit may be implemented in a similar manner including primary inputs and one or more test transistors, each receiving one of the first and second test inputs. A memory device may be configured in a similar manner with address logic that simultaneously asserts the word line signals to test each memory cell of a memory array during an IDDQ test.