Can sub-0.18-um FEOL be realized in production with KrF DUV?

摘要

Abstract: In this paper, (sub) 0.18 $mu@m KrF DUV processes are optimized for logic Front-End-Of-Line (FEOL) CMOS applications. A commercial DUV resist is used without resolution enhancement techniques such as phase-shift masks and off-axis illumination. The full patterning process is considered, i.e., in the final optimized process account is taken of the etch process. Statistical data shows that a stable process was obtained. However, due to minimal process windows at gate level after poly-etch, 0.18 $mu@m FEOL cannot be realized in production with KrF DUV.!5