Modified Conductance Method for The Extraction of Interface Traps in GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors

摘要

This work demonstrates a modified conductance method for the characterization of interface traps in gallium-nitride metal-insulator-semiconductor high electron mobility transistors. It is observed that the defect states cannot be extracted by conventional conductance method in which the capacitance of insulator layer, for instance silicon nitride, is typically selected as the oxide capacitance for conductance calculation. Although the origin remains unclear, it is likely due to the additional effect from aluminum gallium nitride blocking layer that significantly affects the extraction results. A modified equivalent circuit model is proposed accordingly to solve this issue. Additionally, temperature-dependent measurement is carried out to probe the interface traps under different energy levels by our proposed technique.