Comparison of 14 Different Gate Level 1-bit Full Adder Design at Constant Delay

摘要

A full adder is a basic building block and most used circuit that is used as long-chain for different operations and calculating numbers using the cascade of different structures and topology in computer architecture i.e. Arithmetic Logic Unit (ALU). In this paper a trade-off among different parameters like Area acquired, Power used, Quality & Performance (PDP), Energy efficiencies (EDP) of fourteen different full adder circuit is calculated and analyzed at 90nm CMOS technology on DSCH 3.8 software using MICROWIND 3.8 simulator by making a layout of these circuit at constant 27°C temperature and at constant delay and constant voltage to make the analysis simple.