Design of 1-Bit Full-Adder Using Single-Electron CMOS-Inverter-Based AND/OR Gates

摘要

The Single-Electron Inverter (SE-INV) and the Linear Threshold Gate (LTG) are among the basic functional Single-Electron Nano-Devices (SENDs). 1-bit full-adder (FA) cell is the basic block of an arithmetic unit of a digital system. Hence in order to improve the performance of the digital computer system, one must improve the basic 1-bit FA cell. In this paper, the basic element in a SEND, which is the tunnel junction (TJ), and the LTG are reviewed and the conditions for single-electron transport are stated. A detailed analysis of the SE-INV is included. The 2-input CMOS-inverter based AND gate is presented. The multi-input OR gates are implemented using LTG and SE-INV SENDs. The proposed SE 1-bit Full-Adder (FA) is presented. The detailed schematic diagrams along with the corresponding simulation results (using SIMON 2.0) of the SET inverter, the SET AND gate, and the 1-bit SET FA are included. The energy consumption and the delay estimation of the above circuits are calculated. The proposed SE 1-bit FA is compared with those of the previously reported FAs.