FULL-ADDER SUITABLE TO ASIC DESIGN

摘要

PROBLEM TO BE SOLVED: To provide a full-adder with sufficient performance which uses logic cells of a library. ;SOLUTION: Signals A and B are inputted to an exclusive OR circuit 1a and also inputted to an AND part 2b of an AND/NOR circuit. A carry input signal CI and an output signal of the exclusive OR circuit 1a are inputted to an exclusive OR circuit 1b and also inputted to an AND part 2a of an AND/ AOR circuit. A signal (s) is outputted from the exclusive OR circuit 1b and an inverted carry output signal CON is outputted from a NOR part 2c of the AND/NOR circuit. The exclusive OR circuits 1a and 1b are registered as logic cells EO in the cell library respectively and the AND/NOR circuit 2 is registered as a logic cell ANR2 in the cell library.;COPYRIGHT: (C)1999,JPO