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Modeling Static Noise Margin for FinFET based SRAM PUFs

机译:基于FinFET的SRAM PUF的静态噪声容限建模

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In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE simulations. In our experiments, we analyze the impact of process variation, technology, and temperature on the PSNM. The results show that the analytical model matches very well with the simulation model. From the experiments we conclude the following: (1) nFET variations have a larger impact on the PSNM than pFET (1.5% higher PSNM in nFET variations than pFET variations at 25°C), (2) high performance SRAM cells are more skewed (1.3% higher PSNM) (3) the reproducibility increases with smaller technology nodes (0.8% PSNM increase from 20 to 14 nm) (4) increasing the temperature from −10°C to 120°C leads to a PSNM change of approximately 1.0% for an extreme nFET channel length.
机译:在本文中,我们基于紧凑的FinFET晶体管模型开发了一种分析型PUF模型,该模型可计算基于FinFET的SRAM的PUF稳定性(即PUF静态噪声容限(PSNM))。该模型可以快速进行设计空间探索,并可用于识别影响PSNM的关键参数。该分析模型已通过SPICE仿真进行了验证。在我们的实验中,我们分析了工艺变化,技术和温度对PSNM的影响。结果表明,解析模型与仿真模型非常吻合。从实验中我们得出以下结论:(1)nFET变化对PSNM的影响大于pFET(在25°C时,nFET变化的PSNM比pFET变化高1.5%),(2)高性能SRAM单元更偏斜( PSNM高1.3%)(3)技术节点越小,再现性就越高(从20 nm到14 nm,0.8%PSNM增加)(4)将温度从-10°C升高到120°C导致PSNM变化约1.0%以获得极高的nFET沟道长度。

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