The study of low frequency noise of single-walled carbon nanotube transistors

摘要

Nano-scale single-walled carbon nanotube (SWNT) FETs with near ballistic electron and hole transport have attracted interest for potential application in ultra large scale integrated circuits. In addition to immature fabrication technology, hysteresis in the IV characteristics and reported large amplitudes of low frequency noise of SWNT-FETs have impeded their implementation into electronic and sensing systems [1-3]. In this paper, we report a top gate SWNT-FET with reduced hysteresis in the IV characteristics and extremely low 1/f noise. We have also investigated the source of 1/f noise in these devices and attributed the low noise property to low trap charges near the carbon nanotube substrate interface. The SWNT-FET devices reported here and shown schematically in Fig.1(a), are fabricated on high resistivity Si substrate (ρ≈10KΩ) with a 500nm thermal SiO{sub}2. Catalyst patterns are defined by UV photolithography with a 10μm spacing and subsequent iron deposition and lift-off. Single-walled carbon nanotubes (SWNTs) are then synthesized by chemical vapor deposition (CVD) of methane on the substrate using iron catalyst. Source-drain contacts are formed by electron beam deposition of Pd metal. A 20nm high-k HfO{sub}2 film is deposited at 300°C by using HfCl{sub}4 and H{sub}2O precursors in an ASM Microchemistry F-120 ALCVD Reactor. Carbon nanotubes are bridged between source and drain as shown in Fig.1(b). Top Gate metal is defined by UV photolithography followed by the deposition of Cr/Au (10/50nm) with minimum gate length of 1.5μm. Cr/Au (20/450nm) metal interconnects are finally deposited on top of the source and drain Pd contacts.