14nm FinFET technology SRAM cell margin evaluation and analysis by local layout effect

摘要

14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Access Distuib Margin (ADM) response to Local Layout Effect (LLE) as seen in planar CMOS technology using RMG [1]. Additionally, 14nm FinFET technology has more LLEs than ever due to the layout variety or tighter minimum design rule applied [2]. Fluorine with very high reaction energy diffuses from WL CONT to Pass Gate (PG) is found to lower PG Vtsat degrading ß-ratio and ADM. And, the STI stress from strap cell reduces the SRAM NFET Vtsat of the cell at the array edge degrading ADM. The natural variation of Gate-cut to PG degrades the Vth mismatch resulting in ADM degradation also. These three kinds of LLE and their impacts on ADM are discussed and analyzed in detail in this paper along with mechanisms that can cause the LLEs.