SoCs have benefitted immensely from the >1000× linear scaling of Silicon. However, interconnecting die on PCBs has not scaled appreciably in the last several decades and we have had to rely on complex power hungry serializers and deserializers. That is changing now and we show that it can have significant impact on the way we design and integrate complex systems as well as their performance. At UCLA, we have been developing a Simple Universal Parallel IntERface (Super) for the heterogeneous integration of diverse hard IP. Such methods promise to reduce the NRE by 10–20× and reduce the time to market from a few years to a few months, potentially democratizing the chip design and system integration business.
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