Design of low power high speed full adder cell with XOR/XNOR logic gates

摘要

This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor full adder. It is also observed that the delay is reduced by 31.82% for three transistors XNOR gate and 28.76% for eight transistors full adder.