Characterization of self-heating leads to universal scaling of HCI degradation of multi-fin SOI FinFETs

摘要

SOI FinFETs and other Gate-all-around (GAA) transistors topologies have excellent 3-D electrostatic control and therefore, have been suggested as potential technology options for sub-14 nm technology nodes. Unfortunately, the narrow gate geometry and reduced gate pitch suppress heat dissipation and increase thermal cross-talk, leading to severe self-heating of these transistors. Self-heating degrades performance and makes the classical reliability theories based on TL~Tsub irrelevant. In this paper, first, we propose a physics-based thermal circuit compact model for multi-fin SOI FinFETs to characterize self-heating and validate the results by AC conductance method. Next, we analyze HCI degradation varying with the number of fin (Nfin), chuck temperature (Tsub) and AC frequency (f). The results show that HCI degradation dependent variables (NFIN, Tsub, f) can be correlated to the lattice temperature (TL = g(NFIN, Tsub, f)) and obey the universal degradation curve (ΔVth(TL) = f(S(TL) × t)). Si-O bond-dispersion model explains the universal curve; therefore, the model can be used for a long term reliability projection with arbitrary combination Nfin, Tsub, f, etc.