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Deep insight into process-induced pre-existing traps and PBTI stress-induced trap generations in high-k gate dielectrics through systematic RTN characterizations and ab initio calculations

机译:通过系统的RTN表征和从头算起的方法,深入了解高k栅极电介质中的过程诱发的陷阱和PBTI应力诱发的陷阱

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In this work, aiming at comprehensive understandings on pre-existing traps and stress-induced trap generations, HfSiON and HfLaSiON nFETs are comparatively studied by using the constant bias random telegraph noise (cRTN) and the transient RTN (tRTN) characterizations. With La incorporation, low frequency noise is suppressed due to lower deep trap densities while BTI degrades due to shallow traps increasing. More importantly, it is experimentally observed for the first time that PBTI stress will generate deep traps dramatically while shallow traps partly lost simultaneously. Based on the first-principles calculations, underlying mechanisms are discussed and a new model is proposed for PBTI in high-k gate stack nFETs.
机译:在这项工作中,为了全面了解预先存在的陷阱和应力引起的陷阱生成,通过使用恒定偏置随机电报噪声(cRTN)和瞬态RTN(tRTN)表征,对HfSiON和HfLaSiON nFET进行了比较研究。掺入La时,由于较低的深陷阱密度而抑制了低频噪声,而由于浅陷阱的增加而使BTI降低了。更重要的是,首次通过实验观察到,PBTI应力将急剧产生深陷阱,而浅陷阱部分同时消失。在第一性原理计算的基础上,讨论了基本机制,并为高k栅堆叠nFET中的PBTI提出了新模型。

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