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Deep insight into process-induced pre-existing traps and PBTI stress-induced trap generations in high-k gate dielectrics through systematic RTN characterizations and ab initio calculations

机译:通过系统的RTN特性和AB Initio计算,深入了解过程诱导的高k栅极电介质中的预先存在的陷阱和PBTI应力诱导的陷阱世代

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In this work, aiming at comprehensive understandings on pre-existing traps and stress-induced trap generations, HfSiON and HfLaSiON nFETs are comparatively studied by using the constant bias random telegraph noise (cRTN) and the transient RTN (tRTN) characterizations. With La incorporation, low frequency noise is suppressed due to lower deep trap densities while BTI degrades due to shallow traps increasing. More importantly, it is experimentally observed for the first time that PBTI stress will generate deep traps dramatically while shallow traps partly lost simultaneously. Based on the first-principles calculations, underlying mechanisms are discussed and a new model is proposed for PBTI in high-k gate stack nFETs.
机译:在这项工作中,通过使用恒定的偏置随机电报噪声(CRTN)和瞬态RTN(TRTN)特征来竞争地研究了对预先存在的陷阱和应力引起的陷阱世代,HFSION和HFlasion NFET的全面谅解。由于La Incorporation,由于较低的陷阱密度,由于较低的陷阱密度,低频噪声被抑制,而由于浅陷阱增加,因此BTI降低。更重要的是,它首次在实验中观察到PBTI应力将在浅陷阱同时丢失的浅陷阱中产生深陷阱。基于第一原理计算,讨论了基础机制,并在高k门堆栈NFET中提出了一种新模型。

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