T42 - Transputer Design in FPGA (Year Two Design Status Report) Fringe Presentation

摘要

This fringe session will present the design progress of our IMS-T425 compatible Transputer design in FPGA. The 32-bit CPU + Memory interface (2x8kB) are in stable working condition. 117 instructions (from 123+7) are almost implemented in 460 lines of uCode: for example, TASM loops including interruptible MOVE(s) can be simulated some 100 clock cycles. Timer(s) are running. The System control unit allows error mode, MOV-bit and events. Some still open questions around scheduler micro-code and link interaction will be discussed. Slides used in the presentation can be downloaded from [1].