T42 Transputer Design in FPGA (Year One: Design Status Report) Fringe Presentation

摘要

This fringe session will present the current status of our still ongoing IMS-T425 compatible Transputer design in FPGA. Data path and control path are in a stable working state. Fetch unit and a basic system control unit are almost functional. Small instruction sequences can be executed from 8 Kbyte memory already. Some design details around the scheduler micro-code will be discussed. Slides used in the presentation can be downloaded from .