All digital phase locked loop with input clock fail detector

摘要

All Digital Phase Locked Loops are widely used as clock generators in multiprocessor system on chips. An error detection system is crucial for such clock generators since it can be used to notify different processors to shut down so as to prevent the propagation of a faulty clock. In this work, an All Digital Phase Locked Loop with an improved input clock failure detector is presented. The All Digital Phase Locked Loop proposed in this paper is designed to operate from 61KHz to 42Mhz. A completely digital approach is used for the design. The design achieves lock in less than 5 reference cycles. The input clock fail detector circuit detects the loss of input signal and notifies the controller. Fault detection is possible at an early stage and hence, it takes only 2 Digitally Controlled Oscillator clock cycles for stuck at fault detection and 1 reference clock cycle for out of limit fault detection. Entire design is done in Verilog hardware description language and hence it is highly versatile. Synthesis is done using cadence RTL compiler.