The logic gates which reset the digital phase frequency detector of the phase locked loop circuit and resets the digital phase frequency detector of the phase locked loop circuit the manner

摘要

A high reliability phase-locked loop (PLL) is disclosed having a hyperactivity detection and correction circuit (HDC) to oversee the oscillator and the phase and frequency detector (PFD), and having a PFD reset gate that performs the required logic function to reset the PFD while not being vulnerable to an internal PFD race condition that plagues prior art phase-locked loop circuits. The HDC senses the oscillator control and signals an oscillator reset should the oscillator control rise to an abnormally high level above a predetermined limit while the PFD is not detecting the feedback signal. The oscillator reset signal then slowly propagates through an asymmetrical delay line and resets the oscillator control to a predetermined reset state. While the oscillator control is being reset, the HDC continues to monitor the oscillator control, and de-asserts the oscillator reset when the oscillator control drops to the predetermined reset state. The PLL circuit can then function normally to lock on to the reference signal. The HDC incorporates means to prevent an oscillator reset should the PLL lock onto a reference signal having a corresponding oscillator control greater than the predetermined limit, and means to prevent termination of the oscillator reset once the HDC has begun resetting the oscillator control. The PFD reset gate performs the required four input NOR logic function and provides a fast switching reset signal. The PFD reset gate does not de-assert PFD reset until all portions of the PFD have responded to the PFD reset. IMAGE