METHOD FOR RESETTING DIGITAL PHASE/FREQUENCY DETECTOR FOR LOGIC GATE AND PHASE-LOCKED LOOP CIRCUIT

摘要

PURPOSE: To provide a hyper activity detecting and correcting circuit(HDC) for controlling an oscillator (VCO) and a phase-frequency detector(PFD) and to provide a PED reset gate for executing a logic function which is required to reset the PFD, while not having a defect of an inner PFD conflicting condition. ;CONSTITUTION: A HDC 50 senses the control of a VCO 80, and if the oscillator control rises to an abnormally high level beyond a prescribed limit during a feedback signal while a feedback signal has not been detected, the PFD 10 notifies the resetting of the VCO 80 by a signal. Then, the oscillator reset signal slowly propagates via an asymmetric delay line and resets the control of the VCO 80 into a prescribed reset state. During the control of the VCO 80 is reset, the HDC 50 keeps to control the control of the oscillator, and if the control of the VCO 80 falls into the prescribed reset state, if stops the application of the oscillator reset signal. Then, a PLL circuit operates as normal and synchronizes to a reference signal.;COPYRIGHT: (C)1993,JPO