Phase locked loop switching circuit for use in e.g. portable apparatuses, has frequency multiplier comprising clock input and clock output, where loop bandwidth of multiplier is smaller than loop bandwidth of phase locked loop

摘要

The circuit has a frequency multiplier (110) and a phase locked loop (120) comprising respective clock inputs and respective clock outputs, where the phase locked loop has a fractional value. The clock output of the multiplier is electrically connected with the clock input of the phase locked loop, where the loop bandwidth of the multiplier is smaller than the loop bandwidth of the phase locked loop. The multiplier comprises another phase locked loop comprising an integral value. The multiplier comprises adjustable options to adjust the loop bandwidth of the multiplier. An independent claim is also included for a method for configuring a phase locked loop.