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Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector
Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector
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机译:使用全数字频率检测器和模拟相位检测器的频率/锁相环时钟合成器
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摘要
A frequency synthesizer, for integration in a low voltage digital CMOS process, controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls a center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop. The analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This parametric difference allows two separate control inputs to the VCO, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.
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