首页> 外国专利> Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector

Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector

机译:使用全数字频率检测器和模拟相位检测器的频率/锁相环时钟合成器

摘要

A frequency synthesizer suitable for integration in a low voltage digital CMOS process controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls the center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop, thus eliminating any static frequency error. In effect, the analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made much smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This gross parametric difference is used in the design of the VCO to allow two separate control inputs, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.
机译:适用于集成在低压数字CMOS工艺中的频率合成器使用双环路结构(包括模拟环路和数字环路)控制VCO。数字环路包括一个全数字频率检测器,该检测器控制VCO的中心频率。模拟环路包括一个模拟相位检测器和电荷泵,它们可以将相位相干性添加到频率控制环路中,从而消除了任何静态频率误差。实际上,模拟环路可降低数字逻辑和VCO的噪声,数字控制可提供频率保持和非常低的带宽。使数字环路的带宽比模拟环路的带宽小得多,并且优选小200倍。在VCO的设计中使用了这种总的参数差异,以允许两个独立的控制输入,一个来自模拟回路,一个来自数字回路,两个输入相对彼此相对独立。

著录项

  • 公开/公告号US2004223575A1

    专利类型

  • 公开/公告日2004-11-11

    原文格式PDF

  • 申请/专利权人 MELTZER DAVID;BLUM GREGORY;

    申请/专利号US20040796331

  • 发明设计人 GREGORY BLUM;DAVID MELTZER;

    申请日2004-03-08

  • 分类号H03D3/24;

  • 国家 US

  • 入库时间 2022-08-21 22:25:46

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