CMOS digital integrated circuits; LC circuits; circuit feedback; clock and data recovery circuits; equalisers; error statistics; low-power electronics; phase noise; voltage-controlled oscillators; BER; CDR circuit; CMOS; FBB technique; LC-tank VCO; bit error rate; bit rate 25 Gbit/s; clock jitter; complementary metal oxide semiconductor; equalizer; forward-body biasing technique; frequency 25 GHz; low-voltage low-power clock and data recovery circuit; phase noise performance; power 48.8 mW; power consumption; size 65 nm; threshold voltage; two-tank transformer-feedback technique; voltage 0.6 V; voltage controlled oscillator; CMOS integrated circuits; Clocks; Equalizers; Jitter; Logic gates; Transistors; Voltage-controlled oscillators; Clock and data recovery (CDR); equalizer; forward-body bias; jitter; phase noise; transformer-feedback;
机译:具有自适应均衡和波特率时钟以及65nm CMOS技术中的数据恢复功能的60Gb / s 288mW NRZ收发器的设计技术
机译:具有65nm CMOS嵌入式均衡器的26–28-Gb / s全速率时钟和数据恢复电路
机译:具有65nm CMOS工艺的全数字时钟和数据恢复功能的22至26.5 Gb / s光接收器
机译:低压低功耗25 GB / S时钟和数据恢复,具有65 nm CMOS中的均衡器
机译:时钟乘法器单元和时钟数据恢复电路,用于0.18mum CMOS中的10Gb / s宽带通信。
机译:用于汽车压力和温度复合传感器的信号调理IC中采用180 Nm CMOS技术的低功耗小面积符合AEC-Q100标准的SENT发送器的设计
机译:10 Gb / s CMOS串行链路接收器的均衡以及时钟和数据恢复技术